1. Field of the Invention
This invention is directed to the testing of monolithic integrated circuits, particularly complex bipolar transistors. In particular, it relates to test circuits fabricated concurrently with the monolithic circuits. 2. Description of the Prior Art
In the manufacture of semiconductor integrated circuits, it has become common to fabricate test structures during the manufacturing process which serve to yield reliability data on the regular circuits. The principal reason for this is that the integrated circuits themselves cannot be probed because the interconnections of the impurity regions and the devices formed thereby are neither accessible electrically nor can the regions be isolated from one another to provide accurate data. The typical monolithic integrated circuit involves such a dense pattern of impurity regions and metallurgy interconnecting them that the components cannot be readily isolated for testing purposes. Thus, semiconductor designers have found it necessary to design test structures which are isolated from the production circuits which can be tested. One such test site is described, for example, in the patent issued in the names of I. Antipov et al., U.S. Pat. No. 3,507,036, which is assigned to the assignee of the present application.
This type of product-representative structure designed closely to real products requires numerous outgoing contacts, complicated testing and covers too little semiconductor area. Thus, it is relatively ineffective for detecting and monitoring low manufacturing defect levels which are typical of today's products.
The importance of ascertaining and correcting manufacturing defect levels in high density integrated circuits cannot be overemphasized. The defect levels not only affect process yields, but may result in the premature abandonment of a particular process or product in its early stages. Even if such drastic measures do not occur, unchecked defect levels may force systems developers to implement more redundancies and error correction controls, i.e., to redesign around the defect or to cause a recalculation of the acceptable quality levels which are not 100% testable.
It is therefore most important that a product assurance or product test group be able to make continuous in-line measurement of these defect levels during the manufacturing process, enabling the detection of the most important types of defects in order to accumulate know how to sort out the most critical defects and to cure them.
In the above referenced related application of Ghatalia et al., Ser. No. 598,480, there is described a defect monitoring structure employing a series of electrically testable serpentine stripe patterns having different widths and spacings to determine the distribution of defect density. The structure allows the determination of defects such as opens and shorts in diffusions and metallization as well as pin holes in insulation layers. As a defect monitor, the structure measures the primary reliability parameters of relatively simple semiconductor structures, such as field effect transistors. However, the defect monitor described by Ghatalia et al cannot be utilized for monitoring all of the important regions of highly complex integrated circuits such as bipolar transistor circuits, in particular buried regions such as subcollector diffusions, dielectric isolation regions and buried isolation regions.